K JAYARAM KUMAR
@acet.ac.in
Senior Assistant Professor, Department of ECE
Aditya College of Engineering & Technology
EDUCATION
(VLSI Based Signal Processing)
M.Tech (VLSI & Embedded Systems)
B.Tech (Electronics and Communication Engineering
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
E. Jagadeeswara Rao, M. Grace Mercy, K. Jayaram Kumar, M. Rajanbabu, and K. Sudha Ramya
World Scientific Pub Co Pte Ltd
Deepak Kholiya, Mummidi Rachel, Arivarasan S, P. Sukumar, K Jayaram Kumar, and T. Aswini Devi
IEEE
Forest fires are a leading source of ecological destruction. Damage from fires, particularly in their early stages when the system are difficult to see, can be mitigated by a faster and more accurate detection system. Forest fires are a leading source of ecological destruction. Damage from fires, particularly in their early stages when the system are difficult to see, can be mitigated by a faster and more accurate detection system. According to the proposed method, there are three phases, which include model preparation, feature extraction, and training. Unsharp filtering and a CIEXYZ color space conversion are performed on the input image during the preprocessing phase. The boundary chain code, sphericity, and contour line of the fire utilized for feature extraction could constitute the threshold. It utilized a MARK-ELM to train the model. Compared to MARK and ELM, the proposed technique typically obtains a better accuracy of 93.35 percent.
A. Arunkumar Gudivada, K. Jayaram Kumar, Srinivasa Rao Jajula, Durga Prasad Siddani, Praveen Kumar Poola, Varun Vourganti, and Asisa Kumar Panigrahy
Elsevier BV
E. Rao, Durgesh Nandan, R. Rajath Krishna and K. J. Kumar
Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP
Low power and efficient architecture of computer arithmetic is demanded of real time Digital signal processing. Out of all arithmetic units, the multiplier is most important and frequently used arithmetic component in literature. As we know that there are many multipliers exist in the literature and everyone has his own proc-corns. But there is a gap in literature, no one gets compared all popular multiplier technique at same platform and discuss their advantages and limitations at one place. This research work outlines the most popular five multiplier techniques (like Wallace, modified, Vedic, Russian Peasant and Logarithm) and compares them, highlights merits, demerit for further improvements. This comprehensive study includes the systematic development, compares the latest design of every multiplier and justified that which one is better over other reported multiplier is also highlighted.
Kamidi Prasanth, Sabbi Vamshi Krishna, Sanniti Rama Krishna, and Kondapalli Jayaram Kumar
Springer Singapore
P Soundarya Mala, Ch Srigiri, R Jayaram Kumar, and Srivani Vaddi
Diva Enterprises Private Limited
E. Jagadeeswara Rao, T. Ramanjaneyulu, and K. Jayaram Kumar
IEEE
Finite Impulse Response (FIR) filters, microprocessors and digital signal processors are the core system of multipliers. The Multiplier and Accumulator Unit (MAC) is the predominant block in a Digital Signal Processing (DSP) system. The objective of MAC is implementation of signal processing with high performance but multiplier most of the time occupies much area and become power consuming circuits. In this paper, a Modified Russian Peasant Multiplier (MRPM) using Hancarlson adder (HA) has been proposed. According to Russian Rules, a Divide and conquer technique is used in the multiplication process. But, in the perspective of digital design, only shifters and adders are used in the Russian Peasant Multiplier (RPM) to produce a Partial Product Generation (PPG). In this paper, we present an approach towards the reduction of delay in existing RPM by using HA, in the partial product reduction stage and proposed RPM with HA at Partial Product Addition (PPA). The proposed design is also compared to the RPM with Ripple Carry Adder (RCA), Carry Selector Adder (CSA) and 8-2 Adder Compressors (AC) in terms of propagation delay. The proposed design enhances speed of the system by 80.4% compared to the RPM using RCA, 81.7% compared to RPM using CSA and 77.5% compare to RPM with 8:2 adder compressors (AC’s). The total operation is coded with Verilog Hardware Description language (HDL) using Model-Sim 6.3C, synthesized by using the Xilinx Integrated Software Environment (ISE) 14.7 design tool.
E Jagadeeswara Rao, K Jayaram Kumar, and Dr. T. V. Prasad
Science Publishing Corporation
Multiplication is one of the most common arithmetic operations employed in digital systems such as FIR filters and DSP processors but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improv-ing the efficiency of the circuit. High-speed multiplier which uses the high-speed adder is designed based on the Wallace tree concept in this paper. In this paper first we present an approach towards the reduction of delay in Wallace tree multipliers by using 8:2 and 4:2 adder com-pressors, in the partial product reduction stage. The proposed design is also compared to the Wallace Tree multiplier which uses 4:2 and 8:2 adder compressors in terms of propagation delay. The proposed design enhances speed of the system by 74.1% compared to the conven-tional Wallace Tree multiplier, while 24.1 % reduction was achieved in the delay of the system relative to Wallace tree multiplier with 16-bit adder with one of the 8-2 adder compressors.