MUKKU PAVAN KUMAR
@iitgn.ac.in
Electrical Engineering
Indian Institute of Technology Gandhinagar
RESEARCH, TEACHING, or OTHER INTERESTS
Electrical and Electronic Engineering, Computational Theory and Mathematics
FUTURE PROJECTS
In-memory Computing for fast data and computational processing processes and there hardware accelerators
Applications Invited
Scopus Publications
Scholar Citations
Scholar h-index
Scholar i10-index
Scopus Publications
Mukku Pavan Kumar and Rohit Lorenzo
Elsevier BV
Pavan Kumar Mukku and Rohit Lorenzo
Elsevier BV
Pavan Kumar Mukku and Rohit Lorenzo
Elsevier BV
Pavan Kumar Mukku and Rohit Lorenzo
Springer Science and Business Media LLC
Pavan Kumar Mukku and Rohit Lorenzo
IEEE
Space radiation particles causes malfunction in electric circuits. It is especially susceptible to memory-sensitive storage devices. When it affects data stored in the memory circuit, it causes disruption. Standard 6T SRAM is incapable of mitigating this disruption. Consequently, numerous authors presented various resilience strategies. However, a tradeoff exists between memory cell efficiency and soft error probability. This article describes a polar design soft error upset recovery SRAM memory cell (SUR-16T) that effectively recovers lost data due to a high-energy particle strike. SUR-16T has superior write stability, lower hold power dissipation, and shorter write access time at PVT variations compared to the mentioned memory cells. Furthermore, SUR-16T has a 0.96x/ 1.15x/ 1.10x/ 1.18x/ 1.02x/ 1.64x greater critical charge than SEA-14T/ RHBD-13T/ RHMC-12T/ QCCS-12T/ NRHC-14T/ HRRT-13T at 0.8V. In addition, the proposed memory cell demonstrated a higher relative figure of merit than existing memory cells.
Pavan Kumar. Mukku and Rohit. Lorenzo
Institute of Electrical and Electronics Engineers (IEEE)
Mukku Pavan Kumar, Rohit Lorenzo, Junjurampalli Khaja, and Avtar Singh
IEEE
A new PNN-PPN 10T static random access memory (SRAM) cell is presented in this paper. The proposed design aims to address stability of memory cell at worst-case analysis, leakage power analysis, read power analysis and soft error resilience analysis. The proposed design metrics are compared with existing memory cells such as 6T SRAM, feedback control-8T SRAM, low power-9T SRAM, PPN-10T SRAM, schmitt trigger-HT SRAM, low power-8T SRAM. Results observed that the proposed PPN-PNN 10T SRAM improved stability at worst-case analysis, reduces read delay by 0.98x/ 1.08x/ 1.15x/ 1.21x/ 1.15x/ 1.12x times shorter than 6T SRAM/ 8T SRAM/ 9T SRAM/ 10T SRAM/ 11T SRAM/ LP 8T SRAM cells respectively. Moreover, write delay is 1.13x/ 1.06x/ 1.27x times lower than 10T SRAM/ 11T SRAM/ 8T SRAM respectively. Furthermore, leakage power is also reduced. The simulation result shows that the proposed memory cell is suitable for stable and reliable cache memory applications.
Mukku Pavan Kumar and Rohit Lorenzo
Wiley
SummaryOver the past four decades, single event upset (SEU) and single event multiple node upset (SEMNU) have become the major issues in the memory area. Moreover, these upsets are prone to reliability issues in space, terrestrial, military, and medical applications. This article concisely reviews different researchers and academicians who proposed resilience techniques and methods to mitigate this upset mess. In addition, we also investigated the importance of and the impact of on device scaling parameters in upset mechanism, probability of memory failure, and the figure of metrics for the stability of memory cells.
Mukku Pavan Kumar and Rohit Lorenzo
IEEE
In this paper, a 1.2V, radiation-hardened 14T SRAM (RHS-14T) memory cell is proposed to resilience the single event upset (SEU) and dual node upset (DNU) soft errors. The proposed RHS-14T memory cell obtained a 0% failure probability compared to the recently reported radiation-hardened SRAM cells like RSP-14T, RHBD-15T, SAR-14T, SIRI-14T, RH-14T, and SEA-14T with a maximum of 80 fC charge sharing is applied to the sensitive node pairs. The proposed RHS-14T exhibits 2.76x/ 1.43x/ 1.04x/ 1.63x times larger RSNM than RSP-14T/ SAR-14T/ RH-14T/ SEA-14T and 1.18x/ 1.04x/ 1x/ 1.13x/ 1.13x/ 1.21x times larger WSNM than RSP-14T/ RHBD-15T/ SAR-14T/ SIRI-14T/ RH-14T/ SEA-14T. Furthermore, 1.55x/ 1.14x/ 1.12x/ 1.47x/ 1.02x/ 1.54x times larger HSNM than RSP-14T/ RHBD-15T/ SAR-15T/ SIRI-14T/ RH-14T/ SEA-14T. Moreover, 2.06x/ 2.18x/ 1.12x/ 1.01x/ 1.72x/ 1.09x larger effective critical charge than RSP-14T/ RHBD-15T/ SAR-14T/ SIRI-14T/ RH-14T/ SEA14T when supply voltage is at 1V. Results and discussions shows that RHS-14T mitigates a single event upset in all the sensitive nodes. Furthermore, it achieves a better noise margin in terms of write and hold stability in worst-case PVT variations.
Rohit Lorenzo, Sai Naga Snigdha Vajhala, and Mukku Pavan Kumar
IEEE
Memory is an essential element of every VLSI circuit. This paper reviews Content Addressable Memory (CAM) and its conventional architectures. A model of CAM is proposed using a transmission gate (TG). The new design is proposed with 1-bit storing data. The performance of the proposed design is investigated in terms of the following parameters. power, layout area, power delay product (PDP), and transistors count. The design metrics of the circuit are compared at various technology nodes to understand the working better.
Pavan Kumar Mukku, Sushmi Naidu, Divya Mokara, Puthi Pydi Reddy, and Kuppili Sunil Kumar
Springer Singapore